Basic Details Of Debugging In IP/SOC verification
Before start writing in debugging first I will explain design verification in brief. Please find below.
What is verification ?
· Verification
is the process of ensuring that given hardware work as expected.
· Around
70% of the overall design time and cost is spent on verification and validation
· It
becomes very important to verify the correctness of the circuits consisting of
millions of transistors.
· Finding
functional defects in the design process at early stage will help save the cost.
· In short I can say verification is all about
think out of the box.
·
· Verification is all about planning, Strategy,
and approach.
· all you need strong verification plan &
these are just platforms where you execute this plan.
· what matter in the end is how confident you are
in your verification and how many bugs have been reported so far.
· we have gained that confidence that the part of
the design we have verified is perfect in functionality.
· Verilog, SV & UVM is not verification. We need
learn this all things, but along with this we need to prepare our mind to think
creative.
· Because every day we will face new bug, new fix,
new problem.
· I strongly believe that for good verification
engineer we should have good problem-solving skill.
·
Verification
is an art.
Debugging
·
The debugging start when we simulate any
testcase.
·
we should have good knowledge of the tool we are
using us it helps a lot in debugging.
·
a very clear understanding of the features
verified in the respective testcase.
·
Debugging can’t be done without proper design
knowledge.
·
Debugging is based on different types of bugs.
·
As
a Verification Engineer the primary role of yours is Debugging so
that the bugs can be caught and fixed within the Design.
·
Waveform debugging
is also a major skill.
·
Debug is part of any engineer doing any
development work. - be in
Ø
hardware design
Ø
verification
Ø
software development or testing
·
What
is required for debugging?
Ø
It takes lot of skills to be efficient in
debugging
Ø
microarchitecture knowledge,
Ø
testbench and test knowledge, logical thinking, patience,
and perseverance etc. and is a good skill to master first Every other part of a
Verification engineer job (testbench development or test planning etc ) can be
successful only if you overcome this first
·
Following is a diagram from a 2016 study which
shows that most verification engineer spends almost half of his time in debug.
Some Key Points for Good Debug
1. Be patience
2. Go step by step
3. Understand the real flow
4. After that go in depth
5. Use all thing which help to understand the flow & scenario
6. Before going to any decision once think again
7. Understand the priority
Ø Note :- In coming days I will update with example like time out error debug, assertion error debug, OVM/UVM_WRROR debug.
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